Patents

Patents (~60 US Patents)

1. Apparatus and method with homomorphic encryption, W. Choi, J.-W. Lee, E. Lee, Y.-S. Kim, Y. Kim, J.-S. No, J. Lee, US20230188317, filed. 

2. Appratus and method for generating fully homomorphic code, appratus and method for detecting errors of fully homomorphic code, appratus and method for detecting errors of processing of fully homomorphic code, and appratus and method for decoding fully homomorphic code, Y.-S. Kim, Y. Kim, J.-S. No, US2022036851, filed. 

3. Adversarial information bottleneck strategy for improved machine learning, Q. Li, Y. Kim, C. Guyot, US20220138565, filed.

4. Training ensemble models to improve performance in the presence of unreliable base classifiers, Y. Kim, and Y. Cassuto, US11803780, Oct. 2023. 

5. Variable power mode inferencing, Y. Kim, C. Guyot, and W. H. Choi, US11740687, Aug. 2023.

6. Computational resource allocation in ensemble machine learning systems, Y. Kim, Y. Cassuto, R. Mateescu, and C. Guyot, US11487580, Nov. 2022. 

7. Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning, W. H. Choi, Y. Kim, and M. Lueker-Boden, US11216184, Jan. 2022. 

8. Robust detection techniques for updating read voltages of memory devices, Y. Kim, K. Kim, US11163483, Nov. 2021. 

9. Write efficiency in magneto-resistive random access memories, Y. Kim, Y. Jeon, W. H. Choi, C. Guyot, Y. Cassuto, US11031061, Jun. 2021. 

10. Granular refresh rate control for memory devices, Y. Kim, W. H. Choi, C. Guyot, Y. Cassuto, US10991414, Apr. 2021. 

11. Reducing errors caused by inter-cell interference in a memory device, Y. Kim and V. Bhagavatula (B. V. K. Vijaya Kumar), US10199106, Feb. 2019.

12. Error correction for non-volatile memory, R. Mateescu, Z. Z. Vandic, Y. Kim, and S.-H. Song, US9959166, May 2018. 

13. Encoding scheme for 3d vertical flash memory, R. Mateescu, Y. Kim, Z. Z. Bandic, and S.-H. Song, US9830219, Nov. 2017. 

14. Error correction for non-volatile memory, R. Mateescu, Z. Z. Bandic, Y. Kim, and S.-H. Song, US9619320, Apr. 2017.

15. Memory system to determine interference of a memory cell by adjacent memory cells, and operating method thereof, J. Kim, K. Lee, Y. Kim, H. Eun, US9595341, Mar. 2017.

16. Device and method for processing data including generating a pseudo random number sequence, K. J. Lee, J. J. Kong, Y. Kim, J. H. Kim. H. R. Son, J. S. Chung, S. H. Choi, US9158500, Oct. 2015.

17. Data processing systems and methods providing error correction, K. Lee, J. Long, S. Lim, J. Kim, H.-R. Son, Y. Kim, US9100054, Aug. 2015.

18. Methods for operating controllers using seed tables, Y. Kim, J. S. Chung, J. J. Kong, H. Son, US8984036, Mar. 2015.

19. Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit, Y. Kim, J. H. Kim, J. J. Kong, K. L. Cho, US8972775, Mar. 2015.

20. Methods of performing error detection/correction in nonvolatile memory devices, Y. Kim, J. Kong, K. Cho, US8839080, Sep. 2014.

21. Interleaving apparatuses and memory controllers having the same, J. Kim, H.-S. Eun, K.-J. Lee, Y. Kim, US8812942, Aug. 2014.

22. Flash memory system and word line interleaving method thereof, Y. Kim, H. R. Song, S. Choi, J. Kong, US8811080, Aug. 2014. 

23. Semiconductor memory device and data processing method thereof, Y. Kim, J. Kong, J. Kim, H. R. Son, US8806302, Aug. 2014.

24. Flash memory devices, data randomizing methods of the same, memory systems including the same, J. S. Chung, Y. Kim, H. R. Song, J. J. Kong, US8799593, Aug. 2014. 

25. Data storage device and program method that modifies arrangement of program data to eliminate interfering data patterns, Y. Kim, K. L. Cho, H. R. Son, US8782490, Jul. 2014. 

26. Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data, S.-H. Song, J. Kim, K. L. Cho, Y. Kim, J. J. Kong, J. H. Kim, US8773922, Jul. 2014.

27. Storage device having a non-volatile memory device and copy-back method thereof, Y. Kim, H. R. Song, S. Choi, J. Kong, Y. Yim, J. Kim, K. Cho, W. Chang, US8751900, Jun. 2014.

28. Encoding and/or decoding memory devices and methods thereof, J. J. Kong, Y. Kim, J. H. Kim, US8713411, Apr. 2014.

29. Memory device and self interleaving method thereof, S. Choi, H. R. Son, J. Kong, J. Kim, K. Cho, Y. Kim, US8711624, Apr. 2014. 

30. Method for programming non-volatile memory device and apparatuses performing the method, S. H. Choi, H. R. Son, J. J. Kong, Y. Kim, US8711618, Apr. 2014.

31. Method of operating memory controller, and memory system, memory card and portable electronic device including the memory controller, E.-C. Oh, J.-H. Kim, Y. Kim, J.-J. Kong US8689082, Apr. 2014.

32. Method of encoding and decoding multi-bit level data, Y. Kim, J. H. Kim, K. L. Cho, J. J. Kong, K. H. Lee, H. B. Chung, K. S. Choi, US8656258, Feb. 2014.

33. Iterative decoding method and apparatus, J. S. No, B. K. Shin, S. I. Youn, J. D. Yang, J. J. Kong, J. H. Kim, Y. Kim, K. L. Cho, US8607118, Dec. 2013.

34. Methods of performing error detection/correction in nonvolatile memory devices, Y. Kim, J. Kong, K. Cho, US8595601, Nov. 2013.

35. Memory system to determine interference of a memory cell by adjacent memory cells, and operating method thereof, J. Kim, K. Lee, Y. Kim, H. Eun, US8587997, Nov. 2013.

36. Semiconductor device and decoding method thereof, Y. Kim, J.-J. Kong, Y.-H. Lee, J.-H. Kim, US8522124, Aug. 2013.

37. Method of estimating read level for a memory device, memory controller therefor, and recording medium, H. S. Eun, H. R. Son, J. H. Kim, Y. Kim, S. H. Choi, US8516183, Aug. 2013.

38. Data processing system with concatenated encoding and decoding structure, J. Kim, J. Kong, Y. Kim, US8510624, Aug. 2013.

39. Multi-bit cell memory devices using error correction coding and methods of operating the same, Y. Kim, J. Kim, J. Kong, H. R. Son, US8482977, Jul. 2013.

40. Memory device and wear leveling method, Y. Kim, J. H. Kim, K. L. Cho, J. J. Kong, US8473668, Jun. 2013.

41. Nonvolatile memory device, method, system including the same, and operating method thereof, Y. Kim, J. Kim, H. Eun, US8427870, Apr. 2013.

42. Storage device and method for reading the same, Y. Kim, H. Eun, H. W. Yoo, J. Kim, H. R. Son, US8422291, Apr. 2013.

43. Memory systems and defective block management methods related thereto, Y. Kim, J. Kong, J. Kim, H. W. Yoo, US8417988, Apr. 2013.

44. Device and method providing 1-bit error correction, Y. Kim, J. H. Kim, J. J. Kong, US8413011, Apr. 2013.

45. Decoding method and memory system device using the same, J.-S. No, B.-K. Shin, H.-S. Park, Y. Kim, J.-H. Kim, Y.-H. Lee, J.-J. Kong, US8397116, Mar. 2013.

46. Nonvolatile memory device using interleaving technology and programming method thereof, H. S. Eun, Y. Kim, US8391076, Mar. 2013.

47. Non-volatile memory devices, systems, and data processing methods thereof, Y. Kim, J. Kim, J. Kong, US8370710, Feb. 2013.

48. Method of cyclic delay diversity with the optimal cyclic delay value, and transmitter performing the same, T. Noh, B. J. Jeong, H. K. Chung, D. W. Lim, M. J. Lim, H. Y. Kim, Y. Kim, US8364086, Jan. 2013.

49. Data storage system and device with randomizer/de-randomizer, Y. Kim, J. J. Kong, J. H. Kim, K. L, Cho, US8352808, Jan. 2013.

50. Hierarchical decoding apparatus, J. S. No, B. K. Shin, S. I. Youn, J. D. Yang, J. J. Kong, J. H. Kim, Y. Kim, K. L. Cho, US8347194, Jan. 2013.

51. Method of setting read voltage minimizing read data errors, Y. Kim, J. H. Kim, J. J. Kong, H. R. Son, S.-H. Song, US8345487, Jan. 2013.

52. Flash memory device, programming and reading methods performed in the same, H.-s. Eun, J.-h. Kim, J.-h. Kim, D.-h. Chae, S.-h. Song, H.-w. Yoo, J.-j. Kong, Y.-h. Lee, K.-l. Cho, Y. Kim, US8339846, Dec. 2012.

53. Method of estimating and correcting errors in memory cells, J. Kim, Y. Kim, S. H. Song, US8316279, Nov. 2012.

54. Memory devices and encoding and/or decoding methods, Y. Kim, J. H. Kim, J. J. Kong, US8281217, Oct. 2012.

55. Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same, Y. Kim, J.-H. Kim, K.-L. Cho, S.-H. Song, J.-J. Kong, US8274840, Sep. 2012.

56. Memory device and memory programming method, K. L. Cho, Y. D. Park, J. J. Kong, Y. Kim, US8179718, May 2012.

57. Memory device and memory programming method, J. H. Kim, K. L. Cho, Y. Kim, D. H. Chae, US8059467, Nov. 2011.

58. Memory device and method of programming thereof, Y. Kim, K. L. Cho, J. H. Kim, J. J. Kong, H. R. Son, US8004891, Aug. 2011.

59. Memory device and memory programming method, J. H. Kim, K. L. Cho, D. H. Chae, Y. Kim, US7924624, Apr. 2011.

60. Memory device and memory programming method, K. L. Cho, Y. Kim, S.-H. Song, J. J. Kong, US7864574, Jan. 2011.

61. Decoding apparatus for low-density parity-check codes using sequential decoding, and method thereof, S. Kim, Y. Kim, J.-S. No, S.-H. Lee, Y.-H. Kim, J.-Y. Ahn, US7590914, Sep. 2009.